In graphics processing, frame buffers are used to store data that are needed by various graphics processing pipelines. An example of how a processing pipeline interfaces with a frame buffer is illustrated in FIG. 1. As shown in FIG. 1, a processing pipeline 110 receives a transaction 101 to be processed by it. It then reads data required by the transaction 101 from a frame buffer 120 and processes the transaction 101 using the data. After processing is complete, the processing pipeline 110 writes the results into the frame buffer 120. The time taken by the processing pipeline 110 to read data from and write data to memory, such as the frame buffer 120, is respectively known as the read latency and the write latency.
In order to reduce high latencies associated with frame buffer accesses, a cache is employed. The use of a cache is illustrated in FIG. 2. As shown in FIG. 2, a processing pipeline 210 receives a transaction 201 to be processed by it. It then reads data required by the transaction 201 from a cache 230 or a frame buffer 220. If the data is stored in the cache 230, it is read from the cache 230. Otherwise, it is read from the frame buffer 220. The processing pipeline 210 then processes the transaction 201 using the data. After processing is complete, the processing pipeline 210 writes the results into both the cache 230 and the frame buffer 220.
When a transaction depends on the results of a prior transaction, it is held at interlock 240 until the results of the prior transaction are written to the cache 230. Once this is done, the processing pipeline 210 reads that result and processes the transaction. In this particular example, the benefits of using the cache 230 are realized both on the write side (e.g., when the results of the prior transaction are written) and on the read side (e.g., when the results of the prior transaction are read).
The benefits of using a cache, however, are not as great if the processing pipeline latency is significant relative to the cache latency. The time taken by a processing pipeline to process a transaction, known as the processing latency, increases with the depth of the processing pipeline. A transaction that depends on the results of a prior transaction has to wait for the results to be output by the processing pipeline and, in such cases, any speed gains from using a cache are offset by the increased processing latency.